The present invention relates to a semiconductor integrated circuit such as a microprocessor, a semiconductor memory having a redundant circuit, or the like.
In an integrated semiconductor memory such as a mass SRAM (static RAM), a mass DRAM (dynamic RAM) or the like, there are disposed spare cells in addition to normal memory cells (normal cells) in order to relieve defective cells if any. "A 9 ns 1 Mb CMOS SRAM", ISSCC Digest of Technical Papers, pp 34-35, 1989 by K. Sasaki et al. or Japanese Laid-Open Publication No. 2-21500 discloses a spare cell reading method shown in FIGS. 15 and 16.
FIG. 15 is a circuit diagram showing the arrangement of a reading circuit portion in a conventional SRAM. In the arrangement shown in FIG. 15, the memory cells are divided into two blocks, i.e., a first cell array in which n-piece first normal cells 11.1, 11.2, . . . and one first spare cell 21 are connected to a first pair of data lines 31, and a second cell array in which n-piece second normal cells 12.1, 12.2, . . . and one second spare cell 22 are connected to a second pair of data lines 32. Normal word lines 35.1, 35.2, 35.3, 35.4, . . . are disposed for selecting one of 2 n-piece normal cells 11.h, 12.h (h=1 to n) , and spare word lines 37.1, 37.2 are disposed for selecting one of the two spare cells 21, 22.
There is also disposed a decoder 41 for receiving an address. Connected to the decoder 41 are (i) n-piece normal global word lines 33.1, 33.2, . . . the voltage of one of which is raised to a high level in response to an input address, (ii) one spare global word line 36 of which voltage is raised to a high level simultaneously with the one normal global word line above-mentioned, and (iii) first and second block selecting lines 34a, 34b for selecting the cell arrays. In the following description, signals on the n-piece normal global word lines 33.1, 33.2, . . . are respectively designated as NGWL1, NGWL2, . . . , signals on the 2 n-piece normal word lines 35.1, 35.2, 35.3, 35.4, . . . are respectively designated as NWL1, NWL2, NWL3, NWL4, . . . , a signal on the spare global word line 36 is designated as SGWL, signals on the two spare word lines 37.1, 37.2 are respectively designated as SWL1, SWL2, and signals on the first and second block selecting lines 34a, 34b are designated as BLK1, BLK2.
2 n-Piece AND circuits 42.1, 42.2, 42.3, 42.4, . . . are disposed for raising one of the NWLi (i=1 to 2 n) to a high level. Of these, n-piece AND circuits 42.1, 42.3, . . . corresponding to i which is an odd number, are disposed for selecting one of the n-piece first normal cells 11.1, 11.2, . . . in response to NGWLh (h=1 to n) and the BLK1, and n-piece AND circuits 42.2, 42.4, . . . corresponding to i which is an even number, are disposed for selecting one of the n-piece second normal cells 12.1, 12.2, . . . in response to NGWLh (h=1 to n) and the BLK2. AND circuits 44.1, 44.2 are disposed for respectively raising the SWL1 and the SWL2 to high levels. One AND circuit 44.1 is adapted to select the second spare cell 22 in response to the SGWL and the BLK1, and the other AND circuit 44.2 is adapted to select the first spare cell 21 in response to the SGWL and the BLK2. More specifically, when the BLK1 becomes a high level or a logical value 1 (the BLK2 becomes a low level or a logical value 0) and information on one of the first normal cells 11.1, 11.2, . . . is read out onto the first pair of data lines 31, information on the second spare cell 22 is read out onto the second pair of data lines 32. When the BLK2 becomes equal to 1 (the BLK1 is equal to 0) and information on one of the second normal cells 12.1, 12.2, . . . is read out onto the second pair of data lines 32, information on the first spare cell 21 is read out onto the first pair of data lines 31. Information on the first pair of data lines 31 is entered into a first sense amplifier 46.1, and information on the second pair of data lines 32 is entered into a second sense amplifier 46.2.
The first spare cell 21 serves as a substitute cell for the second normal cells 12.1, 12.2, . . . , and the second spare cell 22 serves as a substitute cell for the first normal cells 11.1, 11.2, . . . . A spare address comparing circuit 91 is adapted to judge whether or not a plurality of previously stored or programmed spare addresses contain an address identical with the input address. In the affirmative, it is required to select the first or second spare cell 21, 22 as a substitute cell. In the negative, the input address is called a normal address, requiring no substitute cell. To control the foregoing, the spare address comparing circuit 91 is arranged such that a redundancy judging signal SPARE on an output signal line 92 is set to 1 when a spare address is entered, and that the SPARE is set to 0 when a normal address is entered. When the SPARE is equal to 0, a redundancy judging switch 93 is adapted to supply the BLK1 to the first sense amplifier 46.1 and the BLK2 to the second sense amplifier 46.2, thus activating one sense amplifier 46.1 or 46.2. On the other hand, when the SPARE is equal to 1, the redundancy judging switch 93 is adapted to supply the BLK1 to the second sense amplifier 46.2 and the BLK2 to the first sense amplifier 46.1, thus activating the other sense amplifier 46.2 or 46.1.
According to the arrangement above-mentioned, information of one of the first and second normal cells 11.h, 12.h (h=1 to n) is read out onto an output data line 39 when a normal address is entered, and information of the first or second spare cell 21 or 22 is read out onto the output data line 39 when a spare address is entered. The foregoing is shown in FIG. 16. More specifically, FIG. 16 shows an example where the second normal cell 12.1 selected by the NWL2 is accessed subsequently to the access to the first normal cell 11.1 selected by the NWL1.
First, the NGWL1, the BLK1 and the SGWL are raised by the decoder 41. This causes the NWL1 to be raised to a high level through the AND circuit 42.1 to select the first normal cell 11.1. Simultaneously, the SWL1 is raised to a high level through the AND circuit 44.1 to select the second spare cell 22. At this time, when the input address is a normal address, the SPARE becomes equal to 0. Accordingly, the first sense amplifier 46.1 is activated, causing information of the first normal cell 11.1 to be read out through the first pair of data lines 31. On the other hand, when the input address given for accessing to the first normal cell 11.1, is a spare address, the SPARE becomes equal to 1. Accordingly, the second sense amplifier 46.2 is activated, so that information of the second spare cell 22 instead of the first normal cell 11.1 which is defective, is read out through the second pair of data lines 32. If the second normal cell 12.1 is defective, the first spare cell 21 is used as a substitute cell in a similar manner.
The arrangement in FIG. 15 is adapted such that, in order to read a spare cell at a high speed, one of the NGWL1, NGWL2, . . . and the SGWL are simultaneously raised to high levels before it is judged whether or not the input address is a spare address. However, only one defective cell can be relieved for each cell array, resulting in low defect-relief rate. Japanese Patent Laid-Open Publication No. 2-21500 discloses an arrangement in which a plurality of defective cells in one cell array can be relieved. According to this arrangement, the memory cells are divided into, for example, four blocks (first to fourth cell arrays). It is now supposed that each cell array has n-piece normal cells and three spare cells. By using three spare global word lines and four block selecting lines, there are utilized (i) one spare cell in each of the second to fourth cell arrays as a substitute cell for the first cell array, (ii) one spare cell in each of the third, fourth and first cell arrays as a substitute cell for the second cell array, (iii) one spare cell in each of the fourth, first and second cell arrays as a substitute cell for the third cell array, and (iv) one spare cell in each of the first to third cell arrays as a substitute cell for the fourth cell array. One sense amplifier is prepared for each cell array, and all the voltages of three spare global word lines are raised to high levels simultaneously with the voltage of one of n-piece normal global word lines, regardless of the input address which is a normal address or a spare address.
According to the conventional arrangement above-mentioned in which the defect relief rate is improved, even though the input address is a normal address, it is required that each time an input address is given, there are raised, to high levels, all the voltages of a plurality of spare global word lines in addition to one of the n-piece normal global word lines. This disadvantageously increases the current consumption.
Further, it is required to dispose a plurality of block selecting lines (four lines in the arrangement above-mentioned) in each cell array. This increases the wiring area, causing the chip area to be disadvantageously increased. With an increase in the number of cells which can be relieved in one cell array, the number of block selecting lines passing in each cell array, is increased. This further increases the chip area. Further, it is required to dispose one sense amplifier for each cell array. This also increases the chip area.
When the chip area is increased as a semiconductor memory is increased in capacity, this increases the wiring length of an output signal line for transmitting a redundancy judging signal between the spare address comparing circuit and the redundancy judging switch. This causes the wiring capacitance to be increased, thus provoking a problem of signal delay. Likewise, other conventional semiconductor integrated circuit such as a microprocessor or the like, presents such a problem of signal delay due to wiring capacitance.